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Title:
AUTOMATIC EQUALIZER
Document Type and Number:
Japanese Patent JPS56107623
Kind Code:
A
Abstract:

PURPOSE: To facilitate a miniaturization of hardware constitution for an automatic equalizer, by applying properly a logarithm and exponent transformations to the signal within the automatic equalizer and then replacing the multiplication/division with the addition/subtraction.

CONSTITUTION: The decision 5 is given based on the prescribed presumed value to the result obtained by adding 3 the results obtained by multiplying the tap load by each tap output of the delay line 1 with taps that makes pass the input signals. Then the tap load is controlled in accordance with the result of decision, thus eliminating the intercode interference of the input signal. The multiplication/division between the two signals in such automatic equalizer is carried out by giving the exponent transformation 22 to the result obtained by giving the logarithm transformation 21 and then addition to the two signals.


Inventors:
MATSUSHIMA TOSHIAKI
Application Number:
JP1031180A
Publication Date:
August 26, 1981
Filing Date:
January 31, 1980
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H15/00; H03H21/00; H04B3/04; H04L25/03; (IPC1-7): H03H15/00; H03H21/00



 
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