PURPOSE: To increase the converging speed and the stability after convergence with no increment of the hard quantity for an FIA-type automatic equalizer, by controlling the amount of an integration in accordance with the size of the error signal.
CONSTITUTION: The error signal ek delivered from the subtractor 5 is identified by the identifier 21 and then catches the code to produce sgnek. The delay line 6 with tap produces the signals sgnrk-N∼sgnrkn, and these signals are multiplied by the signal sgnek at the multipliers 7-n...70...7N to produce the signal that shows a code (±or o). On the other hand, the error signal ek is converted into a pulse duration signal through the level/pulse duration converting circuit 22. This pulse duration signal is applied to the AND circuit 230 and the NAND circuit 240 that are shown as the examples for the tap O, and then varies the width of the output signal of the multiplier 70. An integrator consisting of the diodes 250 and 260, the resistance 270, the amplifier 280 and the capacitor 290, each is actuated by the positive output pulse of the circuit 230 and the negative output pulse of the circuit 240. Thus a change is caused to the output of the integrator in accordance with the size of the signal ek.
| JPH0777336 | PROBLEM TO BE SOLVED: To adjust a tap coefficient in an equalizer. |
| JPH01236725 | FILTER |
| JP2536207 | [Title of Invention] Interference Compensator |
OOYAMA TETSUMASA
TAKADA AKIHIKO
