AUTOMATIC LAYOUT METHOD, PROGRAM AND APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

AUTOMATIC LAYOUT METHOD, PROGRAM AND APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JP2007243099

Kind Code:

A

Abstract:

To provide a highly reliable semiconductor integrated circuit by determining the number of contact holes to be arranged and the positional relation of the contact holes with each other by defining the presence region of a hole with the possibility of causing the defect of a metal and turning it to a parameter.

For inputted layout data 101, the number of the contact holes to be used for connection is calculated from the line segment area of the different layer wiring connected with wiring in a contact number calculation part S101, and contacts are generated in a contact generation processing part S102. Thereafter, in a contact correction processing part S103, a contact shape is corrected and layout data 105 after contact generation are output.

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Inventors:

KADOTA TADASHI
KIMURA FUMIHIRO
FUJITA KAZUHISA
MIYASHITA HIROFUMI
TAGUCHI HIROFUMI

Application Number:

JP2006067188A

Publication Date:

September 20, 2007

Filing Date:

March 13, 2006

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L21/82; G06F17/50; H01L21/3205; H01L21/768; H01L23/52

Attorney, Agent or Firm:

Fumio Iwahashi
Hiroki Naito
Daisuke Nagano

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