PURPOSE: To adjust timing of a synchronizing clock accurately and automatically by seeking a reception timing of a proper synchronizing clock based on a deciding output of a data error decision means.

CONSTITUTION: A CPU 70 compares K-sets of fetched serial data with a serial data set to a data transmitter 30 and the number of errors in the K-sets of fetched serial data is measured as data errors when dissidence of even one bit is generated. Then the number of measured errors is displayed on a display device 80 corresponding to a synchronizing clock signal CK1. The CPU 70 executes such processing as above repetitively till a synchronizing clock signal CKn of the final timing. As a result, the number of errors is displayed on the display device 80 corresponding to each of synchronizing clock signals CK1-CKn. Thus, the operator decides which synchronizing clock signal is at a proper timing by observing the display.