PURPOSE: To test the entire circuit normally by implementing insertion and check of a test pattern with an instruction from a call processor and inserting various test patterns to various time slots.

CONSTITUTION: A comparator result outputting gate circuit 10 compares an output of a data latch circuit 2 and an output of a sequential counter 9, that is, a read address of a time division switch memory 8. When they are coincident, a gate pulse being an output of the check result is generated. Moreover, the test pattern and an inserted pattern being an output of a pattern latch circuit 5 are compared by a pattern comparator circuit 11 and the result is sent to a result output circuit 12. Upon the receipt of a gate pulse outputted from the circuit 10, the result output circuit 12 opens a gate and outputs the check result. Thus, the test of the time division switch circuit including the latch memory is conducted automatically continuously.