Title:
AUTOMATICALLY ARRANGING METHOD FOR CELL
Document Type and Number:
Japanese Patent JP3220250
Kind Code:
B2
Abstract:
PURPOSE: To perform the speed-up of an arrangement improving process making any operation to limit the selection of cells not necessary at the time of improving a parallel arrangement, by dividing a chip area into a plurality of slender rectangular regions and simultaneously and parallelly performing the process of interchange of the cells respective regions with a plurarlity of processors, each of which is made to correspond to each different region thereof.
CONSTITUTION: A chip area is cut in the vertical direction to form a slender region which elongates in the direction of the length and cut in the horizontal direction to form a slender region which elongates in the direction of the width, thereby forming a plurality of lengthwise and crosswise rectangular regions. Each different processor P1, P2, P3 is assigned to each of plural slender rectangular regions which are obtained by cutting in the direction of the length. And the improvement of the arrangement of a cell existing within each of the lengthwise rectangular regions to which each processor P1, P2, P3 is assigned is simultaneously and parallely performed within each of the regions so that on the basis of a lengthwise cut-line passing through the inner part of the region, the number of a net passing therethrough is minimized. Thereby, the process of improving the arrangement of a cell with the interchange thereof may be speeded up.
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Inventors:
Toshiaki Ueda
Application Number:
JP23599692A
Publication Date:
October 22, 2001
Filing Date:
September 03, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/82; G06F17/50; (IPC1-7): H01L21/82; G06F17/50
Domestic Patent References:
| JP3225941A | ||||
| JP4113473A | ||||
| JP4139857A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)