Title:
自動初期化型周波数分割器
Document Type and Number:
Japanese Patent JP4965866
Kind Code:
B2
Abstract:
A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other memory element outputs and provides an input to the closed loop system to generate a self-initializing state machine.
Inventors:
Robert H. Miller, Junior
Application Number:
JP2006032705A
Publication Date:
July 04, 2012
Filing Date:
February 09, 2006
Export Citation:
Assignee:
Avago Technologies General IP (Singapore) Private Limited
International Classes:
H03K23/00; H03K23/64
Domestic Patent References:
| JP56165436U | ||||
| JP59210723A | ||||
| JP1303926A | ||||
| JP2223225A | ||||
| JP2223224A | ||||
| JP4274616A | ||||
| JP9307430A |
Attorney, Agent or Firm:
Satoshi Furuya
Takahiko Mizobe
Kiyoharu Nishiyama
Takahiko Mizobe
Kiyoharu Nishiyama