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Title:
AVERAGING FILTER DEVICE
Document Type and Number:
Japanese Patent JPH0435112
Kind Code:
A
Abstract:

PURPOSE: To attain averaging processing with simple constitution by feeding back the output from a delay means to an adder, and extracting the output from the delay means as a filter output.

CONSTITUTION: A filter coefficient from a terminal 13 is multiplied with an input sample data of a terminal 11 by a multiplier 12. The output of the multiplier is supplied to an adder 14, the sum output is supplied to a delay circuit 17 whose delay time is one sample period via a subtractor 16 and the resulting output is fed back to the adder 14 to attain accumulation. The output of the circuit 17 is extracted from a terminal 18 as an averaged output data of (2m+1) sets of sample. The output data of the multiplier 12 is fed to the subtractor 16 as a subtractor input via a circuit 15 having a delay time in response to the number of data to be averaged. Thus, after the averaging processing, the delay output data is sequentially subtracted from succeeding integration data to average (2m+1) sets of samples.


Inventors:
ROBAATO JIYON DEBITSUDO ROORA
Application Number:
JP13566690A
Publication Date:
February 05, 1992
Filing Date:
May 25, 1990
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03H17/02; H03H17/06; (IPC1-7): H03H17/02
Attorney, Agent or Firm:
Akira Koike (2 outside)



 
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