Title:
半導体装置用のバックエンド工程伝送線路構造(バックエンド工程処理におけるサスペンデッド伝送線路構造の形成方法)
Document Type and Number:
Japanese Patent JP4776618
Kind Code:
B2
Abstract:
A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.
Inventors:
Chin Takindi, Anneal, K
Groves, Robert, A
Trettier Cove, Yori, Vi
Vaed, Knorr
Voland, Richard, Pea
Groves, Robert, A
Trettier Cove, Yori, Vi
Vaed, Knorr
Voland, Richard, Pea
Application Number:
JP2007510982A
Publication Date:
September 21, 2011
Filing Date:
April 28, 2005
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L23/522; H01L21/4763; H01L21/768; H01P11/00; H01L23/532
Domestic Patent References:
| JPH11248410A | 1999-09-17 | |||
| JP2005514728A | 2005-05-19 | |||
| JPH11204637A | 1999-07-30 | |||
| JP2003243500A | 2003-08-29 | |||
| JP2002533954A | 2002-10-08 |
Foreign References:
| US20030173633A1 | 2003-09-18 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi