PURPOSE: To prevent erroneous data from being written in a nonvolatile memory by providing an interruption processing means, a reset processing means and an address bus control means.

CONSTITUTION: This device is constituted by providing an interruption processing means for applying an interruption processing to a central processing unit (CPU) 11, a reset processing means for applying reset to the CPU 11, and an address bus control means for setting the most significant bit of an address bus to '0' so that an address allocated to a memory 12 is not selected. In this case, when a power supply voltage becomes a voltage being between a voltage for which write protection of the memory 12 and a normal power supply voltage, the instruction is applied to the CPU 11, and when the voltage becomes a voltage being the between this interruption voltage VT and the voltage for which the write protection of the memory 12 is applied, reset is applied to the CPU 11, and also, the most significant bit of the address bus is set to '0' so that the address allocated to the memory 12 is not selected. In such a manner, it can be prevented that erroneous data is written in a nonvolatile memory 13.