PURPOSE: To decrease the number of elements of a balance/unbalance conversion circuit by synthesizing two current signals at the input side of a circuit which converts a balance voltage signal into a current signal and omitting a current synthesizing current mirror circuit.
CONSTITUTION: The input signal voltage of terminals I1 and I2 are set at V1+ v1 and V2+v2 respectively (V: DC bias component, v: AC signal component). While the current amplification factor of a current mirror CM1 is set at mi. The base voltage VB4 of a transistor TRQ4 is shown by an equation I , and an equation II shows the voltage drop amount VR4 of an R4 caused by the output current of the CM1. An equation III shows a current output signal I0' of an output terminal 0. Therefore an AC signal proportional to (v2-v1) is obtained by setting m1=1, R1=R2 and R11=R3=R4, respectively. In other words, an unbalance signal is obtained and a current synthesizing current mirror circuit is omitted.
TANABE MASAAKI
HAYASHI TOSHIO
KIMURA TADAKATSU
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