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Title:
BALANCED RECEIVING CIRCUIT
Document Type and Number:
Japanese Patent JPS58141038
Kind Code:
A
Abstract:

PURPOSE: To obtain an output signal in which unbalanced noise is suppressed considerably at each stage, by providing a mid-point terminal to the secondary winding of a transformer and grounding the mid-point terminal through the grounding terminal of a balanced input type amplifier.

CONSTITUTION: The majority of unbalanced noises entering the secondary windind side through an interwinding electrostatic capacitor is grouned directly through the mid-point terminal 25, so unbalanced noises appearing between terminals 23 and 14 and the ground are reduced greatly. Further, a few remaining unbalanced noises have every small amplitude, so they are removed through the balanced input type amplifier 3. The ground impedance of the balanced input type amplifier 3 viewed from the terminals 23 and 24 is not influenced at all because of the grounding of said mid-point terminal 25, so the amplifier operates normally to output no unbalanced input noise to an output terminal 51. Said grounding of the mid-point terminal 25 causes a triffle increases in the amount of unbalance input noises converted into balanced noises through the transformer 2 itself, but noises outputted to the output terminal 51 are reduced.


Inventors:
SHIGAKI SEIICHIROU
Application Number:
JP2275882A
Publication Date:
August 22, 1983
Filing Date:
February 17, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H7/42; H04B1/10; H04B1/18; H04B3/30; H04B3/32; H04L25/08; (IPC1-7): H03H7/42; H04B1/10; H04B1/18; H04L25/08
Attorney, Agent or Firm:
Uchihara Shin (1 person outside)



 
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