Title:
BARE CHIP LSI MOUNTING STRUCTURE
Document Type and Number:
Japanese Patent JP2973646
Kind Code:
B2
Abstract:
PURPOSE: To provide a bare chip LSI mounting structure where a bare chip LSI is directly mounted on a multilayered circuit board as sealed and which is lessened in size and enhanced in mounting density, heat dissipating property, and EMI countermeasure.
CONSTITUTION: The mount of a multilayered circuit board 1 where a bare chip LSI 9 is mounted is formed into a stepped recess 2, an inner plane spreading wide is provided to the base of the recess, an inner conductor 3 where the LSI 9 is die-bonded is exposed, circuit terminals 4 connected to the bare chip LSI 9 are provided to steps 21 at opposed positions through an inner conductor. A ring-shaped conductor pattern 11 connected to a ground circuit is provided to the surface edge of the stepped recess 2, the stepped recess 2 is covered with a cap 5 provided with a full conductor plane 51 formed on one side and an insulated circuit pattern 52 formed on the other side, the inside of the stepped recess 2 is sealed up by bringing the full conductor plane 51 into close contact with the conductor pattern 11, and the circuit pattern 52 is connected to the surface circuit pattern 12 of the circuit board 1.
Inventors:
TSUBONE KENICHIRO
KURODA YASUHIDE
TAKABAYASHI HIROYUKI
KURODA YASUHIDE
TAKABAYASHI HIROYUKI
Application Number:
JP26659691A
Publication Date:
November 08, 1999
Filing Date:
October 16, 1991
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H05K1/14; H01L23/12; H05K1/18; H05K3/34; (IPC1-7): H05K1/18; H01L23/12
Domestic Patent References:
| JP6413755A | ||||
| JP63194350A |
Attorney, Agent or Firm:
Teiichi