PURPOSE: To reduce the capacity of a battery greatly by inhibiting undesired writing to a memory chip during a failure or a commercial power source.

CONSTITUTION: In case of a temporary failure of the commercial power source AC, the voltage of a DC power source 1 which is not supported by a battery is ceased. As a result, a power supply voltage is applied to none of the writing circuit 7 and reading circuit 8 of a CPU2 and read data buffer 14 and write data buffer 15, and neither writing nor reading is carried out. Then, the voltage at the connection point A between resistances 21 and 22 of the multiplexer and timing circuit 10 of the CPU2 is ceased and a transistor 20 turns off. Then, the output point C of a gate 19 is held at a low potential. Consequently, even if a timing generating circuit 17 generates a signal WE erroneously, the output signal WEM of a read data buffer 18 is "0" to prevent undesired writing to the memory chip 11 (nonvolatile memory) of a main storage device 3.