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Patent Searching and Data


Title:
BCH CODE DECODING SYSTEM
Document Type and Number:
Japanese Patent JPH03183217
Kind Code:
A
Abstract:

PURPOSE: To execute correct error correction without executing phase uncertainty removal in a shortened BCH code decoding system by making an excess bit not to be transferred equal to one optional bit of information bits.

CONSTITUTION: The excess bit not being used in one frame is made equal to one optional bit among the information bits, and is encoded by a division part 50 and a check bit addition part 60, and is sent to a transmission line. At a receiving side, received data from the transmission line is divided by a syndrome calculation part 10, and a syndrome is calculated. Then, when a special code detecting means 11 detects a special code from a calculated result, it sends a control signal showing that it detected the special code to a designated bit correcting means 31. The designated bit correcting means 31 becomes capable of executing the correct error correction without executing the phase uncertainty removal by correcting the error of the designated bit.


Inventors:
YUKI HIROYUKI
Application Number:
JP1989000322961
Publication Date:
August 09, 1991
Filing Date:
December 12, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M13/00; (IPC1-7): H03M13/00