Title:
BEAR CHIP MOUNTING CIRCUIT DEVICE AND ITS HIGH POWER SUPPLY VOLTAGE IMPRESSION TEST METHOD
Document Type and Number:
Japanese Patent JP2006322786
Kind Code:
A
Abstract:
To provide a bear chip mounting circuit device capable of safe and highly accurate high power supply voltage impression tests of IC chips to be inspected, and to provide its test method.
When a tester 200 impresses a power terminal 30 of a microprocessor 3 with a power supply voltage Vt for test higher than its power supply voltage through a substrate power line 20, an output terminal of an IC chip 4 built in a power circuit for impressing the microprocessor 3 with the power supply voltage is normally cut off into a floating potential state by transistors 44 and 47 to prevent the power supply voltage Vt for test from flowing to the IC chip 4 built in a power circuit and other circuit elements.
Inventors:
HAYAKAWA TOMOHARU
NISHIMURA TOSHIRO
KABUNE HIDEKI
NISHIMURA TOSHIRO
KABUNE HIDEKI
Application Number:
JP2005145505A
Publication Date:
November 30, 2006
Filing Date:
May 18, 2005
Export Citation:
Assignee:
DENSO CORP
International Classes:
H01L21/822; G01R31/28; H01L27/04
Domestic Patent References:
| JPS61189473A | 1986-08-23 | |||
| JPS6428858A | 1989-01-31 | |||
| JP2000209847A | 2000-07-28 | |||
| JP2004260090A | 2004-09-16 | |||
| JP2002298599A | 2002-10-11 |
Foreign References:
| WO2002075341A1 | 2002-09-26 |
Attorney, Agent or Firm:
Hiroshi Okawa