Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP2565098
Kind Code:
B2
Abstract:
PURPOSE: To reduce capacitance between wirings and a substrate and to suppress a recess of a non-element region occurring by polishing of an insulting film to be used in the step of burying an insulator by forming all a buried silicon oxide film of the SOI(silicon-on-insulator) substrate of the non-element region of an insulator.
CONSTITUTION: An insular single-crystal silicon layer 3 is formed on an element region 5 on a silicon substrate 1 having the layer 3 formed through a silicon oxide film 2. A silicon oxide film 8 is deposited on the entire surface, polished to be flattened, a silicon nitride film 4 is removed, and an emitter region 3c, a base region 3d and a collector region 3e of a semiconductor element are formed on the layer 3 of the region 5. Thus, since a non-element region 6 is all buried with the film 8 of an insulator, capacitance between a wiring region, a resistor and the substrate can be reduced.
Inventors:
SUGYAMA MITSUHIRO
Application Number:
JP19512093A
Publication Date:
December 18, 1996
Filing Date:
July 12, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/762; H01L21/76; H01L27/12; (IPC1-7): H01L21/762; H01L27/12
Domestic Patent References:
| JP482249A | ||||
| JP63181443A | ||||
| JP258873A |
Attorney, Agent or Firm:
Noriaki Miyakoshi