Title:
BIAS CIRCUIT
Document Type and Number:
Japanese Patent JP2008177987
Kind Code:
A
Abstract:
To reduce bias deviation in a case where a current increases during an FET active state.
In accordance with a gate voltage of the FET, a base potential of a transistor provided in parallel with a resistor for drain current detection is controlled.
Inventors:
HIROSAKA SHIRO
Application Number:
JP2007011215A
Publication Date:
July 31, 2008
Filing Date:
January 22, 2007
Export Citation:
Assignee:
NEC CORP
International Classes:
H03F3/193; H03F3/24
Attorney, Agent or Firm:
Iat International Patent Business Corporation
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