Title:
Bias circuit
Document Type and Number:
Japanese Patent JP5937144
Kind Code:
B2
Abstract:
One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
Inventors:
Hiroki Inoue
Kiyoshi Kato
Shuhei Nagatsuka
Koichiro Kamata
Tsutomu Murakawa
Takahiro Tsuji
Ika Kaori
Kiyoshi Kato
Shuhei Nagatsuka
Koichiro Kamata
Tsutomu Murakawa
Takahiro Tsuji
Ika Kaori
Application Number:
JP2014123707A
Publication Date:
June 22, 2016
Filing Date:
June 16, 2014
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G05F1/56; G05F3/26; G06K19/07
Domestic Patent References:
| JP2008165286A | ||||
| JP9179646A | ||||
| JP54114981A |