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Title:
BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPS58141012
Kind Code:
A
Abstract:

PURPOSE: To reduce variation of circuit characteristics of a bias circuit for the base bias of an integrated by using a current mirror circuit as said bias circuit and stabilizing a bias voltage against fluctuations of temperature without variance.

CONSTITUTION: The 1st and the 2nd resistances 37 and 38 for voltage division are cascaded between a power terminal 19 and an earth terminal 20; and the base of the 1st TR29 is connected to the mutual connection point between those resistances 37 and 38 and the collector is connected to the earth terminal 20. An error component ΔV due to a difference in VBE is caused principally by relative variance ΔVBE of the VBE of each pair TR and variation in the ratio between the emitter current of a TR34 and that of a TR33 with variation in mirror ratio with current amplification factors hFE of TRs 35 and 36 and with variation of the base current of the TR34 with the factors hFE. When the lower-limit values of the factors hFE of both NPN and PNP TRs are both 50, the current ratio is 0.92 for the lower-limit values and the VBE of three TRs is about -6.5mV. Then when the ΔVBE of the pair TRs is ±0.5mV, its variation is random, so it is about ±0.9mV after squaring and averaging, so that the variance is reduced approximately by one figure.


Inventors:
OONISHI MASAMI
Application Number:
JP2380982A
Publication Date:
August 22, 1983
Filing Date:
February 16, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03F1/30; (IPC1-7): H03F1/30
Attorney, Agent or Firm:
Toshio Nakao



 
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