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Title:
BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPS6139606
Kind Code:
A
Abstract:

PURPOSE: To remove the occurrence of abnormal phenomena such as oscillation of a semiconductor element etc. by constituting a DC bias line to attain a terminal of resistance in a low frequency band other than a signal frequency.

CONSTITUTION: A lead wire from a through type porcelain condenser 4 that applies voltage of -VG to the gate terminal of an FET1 to a 1/4 wavelength resonator 3 is covered with a ferrite core of large magnetic loss. Utilizing the fact that a ferrite element acts as an absorbing body in low frequency, impedance looked from a connecting point 11 to the through type condenser 4 side is made to be regarded as a terminal of resistance nearly conformable to impedance looking the FET1 side in frequency other than a signal frequency. Constitution is the same in the case where voltage of +VD is applied to the drain terminal of the FET1. Thus, abnormal phenomena such as the occurrence of oscillation of a semiconductor element such as an FET which is generally high gain in low frequency band can be prevented.


Inventors:
OKAZAKI KATSUHIRO
Application Number:
JP16041784A
Publication Date:
February 25, 1986
Filing Date:
July 30, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03F1/08; H01P1/00; H03F3/60; (IPC1-7): H03F1/08; H03F3/60
Domestic Patent References:
JPS541698B11979-01-27
JPS4838198A1973-06-05
JP57140713B
Attorney, Agent or Firm:
Yutaro Kumagai