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Title:
BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPS6373710
Kind Code:
A
Abstract:

PURPOSE: To prevent increase in current consumption corresponding to the band setting of an operational amplifier used for a switched capacitor filter by generating a bias voltage in response to a frequency of a drive clock.

CONSTITUTION: When switches 101, 102 repeat conduction/non-conduction alternately by the clock having a frequency fc, the electric charge Q applied to a transistor (TR) 104 by one switching is expressed as Q=C.V0, where V0 is a drain voltage, that is a potential at an output terminal 105 and C is a capacitance of a capacitor 103. Thus, the mean current I flowing the TR 104 is expressed as I=fc.Q=fc.C.V0. That is, switches 101, 102 and the capacitor 103 act like an equivalent resistance R (R=V0/I=I/fc.C) inversely proportional to the clock frequency.


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Inventors:
MORITO HIROSHI
Application Number:
JP21837786A
Publication Date:
April 04, 1988
Filing Date:
September 16, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Attorney, Agent or Firm:
Uchihara Shin



 
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