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Title:
BICMOS CIRCUIT
Document Type and Number:
Japanese Patent JPH06314966
Kind Code:
A
Abstract:

PURPOSE: To provide a new BiCMOS circuit operated at a higher speed than a conventional BiCMOS circuit in which higher speed operation is attained than a CMOS circuit even under a low power supply voltage of 3.3V or below.

CONSTITUTION: The circuit consists of an npn bipolar transistor(TR) 3 and a p-channel field effect TR 5, a collector of the NTN type bipolar TR 3 connects to a high level power supply terminal 1 via a load 6, its base is connected to an input terminal 4, and its emitter is connected to a low level power supply terminal, and a source and a gate of the p-channel field effect TR 5 are connected to the input terminal 4 and its drain connects to a low level power supply terminal 7. When the bipolar TR is nonconductive, since the base potential is kept to a potential level higher than the emitter potential by a turn-on voltage of the field effect TR, the time when the bipolar TR is turned on is considerably decreased and the circuit is operated at a high speed even under a voltage below 3.3V in comparison with the operation speed of a CMOS circuit of the same process.


Inventors:
KIMURA TORU
Application Number:
JP5664293A
Publication Date:
November 08, 1994
Filing Date:
March 17, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/06; H01L21/8249; H03K17/56; H03K17/567; H03K19/08; (IPC1-7): H03K19/08; H01L27/06; H03K17/56
Domestic Patent References:
JPH01137822A1989-05-30
JPH04104612A1992-04-07
JPH04142115A1992-05-15
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)