Title:
BICMOS MULTIPLEXER, LOGICAL GATE AND ADDER BASED THEREON
Document Type and Number:
Japanese Patent JPH06237160
Kind Code:
A
Abstract:
PURPOSE: To obtain a BiCMOS multiplexer, having differential inputs and differential outputs by constituting the multiplexer, so that the multiplexer has noninverted and inverted inputs of a first differential input, a second differential input, and a differential selective input and may give signals at the output corresponding to the first or second differential input, based on a selective input. CONSTITUTION: A multiplexer 10 is composed of four single n-type MOS pass gates 12, 14, 16, and 18, two npn-type bipolar transistors 22 and 26, two n-type MOS transistors 34 and 38, and two p-type MOS transistors 43 and 47. The multiplexer 10 contains the noninverted and inverted inputs (d0 and d0' and d1 and d1') of two differential inputs and the inputs d1, d0, d1' and d0' are respectively given to the first source/drain elements of the transistors 12, 14, 16, and 18. Noninverted selective inputs S are given to the gate electrodes of the n-type MOS transistors 14 and 18, and inverted selective input signals S' are give to the gate electrodes of the transistors 14 and 18.
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Inventors:
TOOMASU DEIRU FURETSUCHIYAA
EDOWAADO ARIN BAATON
EDOWAADO ARIN BAATON
Application Number:
JP41824290A
Publication Date:
August 23, 1994
Filing Date:
December 25, 1990
Export Citation:
Assignee:
PHILIPS NV
International Classes:
G06F7/505; G06F7/50; G06F7/501; G06F7/503; G06F7/506; H03K17/00; H03K17/567; H03K17/693; H03K19/08; H03K19/0944; H03K19/20; H03K19/21; (IPC1-7): H03K17/56; G06F7/50; H03K17/00; H03K19/08
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)
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