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Title:
BINARIZATION PROCESSOR
Document Type and Number:
Japanese Patent JPS62108380
Kind Code:
A
Abstract:

PURPOSE: To obtain binary images having different threshold at high speed and with a low hardware cost by providing an address memory part, and applying a binarization process only to a data to which the variable density image data has an intermediate value.

CONSTITUTION: At an initial stage, switches 6 and 104 are connected to an A side, and an address generator 4 is connected to a variable density image memory 1 and a binary image memory 3, and an address memory 103. The second address generator 102 is connected to the second table memory 101. Furthermore, the first table memory 2 is set so that the threshold of a binarization can be a value t1 other than an intermediate value D, for example, black, and the second table memory 101 is set so as to generate an output when the variable density data is the intermediate value E. An address signal is given from the generator 4 to the memory 1, and the variable density image data is read out. The data is sent to the memory 2, and is converted to a binary image data, and is stored on the memory 3 with the address signal from the generator 4.


Inventors:
ENDO KOICHIRO
Application Number:
JP24921785A
Publication Date:
May 19, 1987
Filing Date:
November 07, 1985
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04N1/40; G06K9/38; (IPC1-7): G06K9/38; H04N1/40
Attorney, Agent or Firm:
Toshio Nakao



 
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