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Patent Searching and Data


Title:
BINARY CODING DEVICE
Document Type and Number:
Japanese Patent JPS6072376
Kind Code:
A
Abstract:

PURPOSE: To facilitate setting of a binary coding level and to make binary coding stable and high-speed by giving a function of adjusting a specified number of potentiometers to simple circuit configuration and performing correction of shading and correction of uneven illumination carefully.

CONSTITUTION: An initial address is generated by an address generating circuit 11 of a binary coding device at the time of starting fetching-in of a picture. Thereafter, an address is generated while adding 1 by a specified clock, and addresses for a specified number of times are generated. The circuit 11 is forcibly shunted by a microprocessor 12, and a bus of the circuit 11 for circuit after an RAM14 or a bus of the processor 12 is made effective by an instruction of the processosr 12 in a selecting circuit of the bus. An output of the RAM14 is added to D/A converters 161, 162 through latch circuits 151, 152 and digitized. Respective outputs are relative operated in a relative operating section 17. Thus, setting of the binary coding level is made easy and a binary coding output is outputted stably and at high speed.


Inventors:
NAITOU SHIMON
Application Number:
JP18001783A
Publication Date:
April 24, 1985
Filing Date:
September 28, 1983
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H04N1/403; H04N1/40; H04N19/00; (IPC1-7): H04N1/40; H04N7/13
Attorney, Agent or Firm:
Iwao Yamaguchi