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Title:
BINARY-ENCODING SYSTEM FOR ANALOG SIGNAL
Document Type and Number:
Japanese Patent JPS5724119
Kind Code:
A
Abstract:

PURPOSE: To binary-encode the profile of a pattern even for a signal with less contrast, by shifting an input analog signal with two different levels after delaying it to form the slice level.

CONSTITUTION: The resing and falling time of an input analog signal 10 are delayed to the same degree with a delay line 2. A delayed signal 11 is level-shifted toward positive and negative direction with level shift circuits 3, 4 and applied to comparators 5, 6. The input analog signal 10 is applied to another end of the comparators 5, 6 to detect the edges of the input analog signal 10. An edge signal delayed with a delay circuit 7 and an edge signal 14 are applied to a pulse conversion circuit 9 via and OR gate 8 to be a binary-encoded signal 18 with a given width. The delay circuit 7 is to prevent the production of two pulses for one edge.


Inventors:
KURIHARA KENJI
Application Number:
JP9762880A
Publication Date:
February 08, 1982
Filing Date:
July 18, 1980
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K5/1532; H03K5/08; (IPC1-7): H03K5/08
Domestic Patent References:
JPS4722060A