PURPOSE: To binary-encode the profile of a pattern even for a signal with less contrast, by shifting an input analog signal with two different levels after delaying it to form the slice level.
CONSTITUTION: The resing and falling time of an input analog signal 10 are delayed to the same degree with a delay line 2. A delayed signal 11 is level-shifted toward positive and negative direction with level shift circuits 3, 4 and applied to comparators 5, 6. The input analog signal 10 is applied to another end of the comparators 5, 6 to detect the edges of the input analog signal 10. An edge signal delayed with a delay circuit 7 and an edge signal 14 are applied to a pulse conversion circuit 9 via and OR gate 8 to be a binary-encoded signal 18 with a given width. The delay circuit 7 is to prevent the production of two pulses for one edge.
JPH01241914 | GENERATOR FOR PULSE IN RESPONSE TO VOLTAGE CHANGE |
JPS57183121 | FAIL-SAFE TYPE DIFFERENTIATING CIRCUIT |
JPS4722060A |