Title:
BINARY MULTIPLICATION REALIZED BY EXISTENT HARDWARE AFTER SMALL CORRECTION
Document Type and Number:
Japanese Patent JP3519765
Kind Code:
B2
Abstract:
PURPOSE: To execute binary multiplication by means of existent data processor by necessitating only small correction.
CONSTITUTION: A first operand and a partial product are housed in the existent latch of CPU. A second operand is housed in a shift register 73 and added to CPU. Concerning data within the shift register 73, '0' is loaded within a lowest-order bit LSB and data is shifted to a highest-order bit MSB from LSB. When the bits of the first operand is successively designated and the designated bit is '1', the value of the partial product is increased by a value within the shift register 73. After this order control designates all the bit of the first operand, the partial product is obtained as the product of multiplication.
Inventors:
Intrater, Gideon
Falik, Ohad
Ostrer, Aharon
Baydatch, Yair
Erlich, Gadi
Falik, Ohad
Ostrer, Aharon
Baydatch, Yair
Erlich, Gadi
Application Number:
JP31229993A
Publication Date:
April 19, 2004
Filing Date:
December 13, 1993
Export Citation:
Assignee:
NATL SEMICONDUCTOR CORP <NS>
International Classes:
G06F7/52; G06F7/53; G06F7/523; G06F7/72; G06F9/302; (IPC1-7): G06F7/52
Attorney, Agent or Firm:
古谷 馨 （外２名）
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