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Title:
BINARY PICTURE MULTI-VALUING AND REDUCING PROCESSOR
Document Type and Number:
Japanese Patent JPH1011571
Kind Code:
A
Abstract:

To obtain a binary picture reducing processor for speedily realizing the processing of reducing a binary picture by making multilevel by minimum number of arithmetic times whatever filter is used.

A 2N:1 multi-valuing and reducing part 14 filters the binary picture expressed by one pixel and one bit through the use of a filter for 2:1 reduction to generate multilevel to accelerate processing until reducing an inputted picture to 2:1. In addition, the processing is repeated by the number of times (N-1 times) decided by a thinning rate dividing control part 12 to generate an M-level picture of 2N:1 reduction to generate an M-level reduced picture by small number of product sum arithmetic times. In addition, an additional reducing processing part 17 reduce-processes the picture generated by the part 14 by the magnification decided by the part 12 to generate the M-level reduced picture of an inputted and desired magnification.


Inventors:
ATSUMI EIJI
Application Number:
JP16003396A
Publication Date:
January 16, 1998
Filing Date:
June 20, 1996
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06T3/40; G06T5/00; H04N1/40; H04N1/393; (IPC1-7): G06T5/00; G06T3/40; H04N1/393; H04N1/40
Domestic Patent References:
JPH0540825A1993-02-19
JPH07264395A1995-10-13
JPS6045290A1985-03-11
JPS567543A1981-01-26
JPS567544A1981-01-26
JPS55114050A1980-09-03
JPH03289267A1991-12-19
Attorney, Agent or Firm:
Kaneo Miyata (3 outside)