To reduce a bit length of a frame synchronizing signal and to eliminate restriction of a data pattern by replacing a synchronization flag in precedence over biphase data with a non-change part by 2 clocks at a transmitter side and sending the simplified synchronization flag.

A data transmission section 11 of a transmitter side 1 gives differential biphase code data f1 and a frame synchronizing signal f2 in precedence over the differential biphase code data f1 to a non-change part generating circuit 12. The non-change part generating circuit 12 inserts a non-change part by 2 clocks as a synchronization flag of the frame synchronizing signal f2 to the differential biphase code data f1 and sends the result as differential biphase code data f3. Thus, number of bits for frame synchronization detection is reduced and no flag pattern is detected, then complicated operation such as zero removal is not required and restriction of a data pattern is avoided.