Title:
BIPOLAR CLOCK DISTURBANCE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP2988300
Kind Code:
B2
Abstract:
PURPOSE: To realize a bipolar clock disturbance detection circuit in which the disturbance of a bipolar clock is surely detected.
CONSTITUTION: A bipolar clock disturbance detection circuit is made up of a unipolar signal extract means 1, a 1st abnormality discrimination means 3, a 2nd abnormality discrimination means 5, and an OR circuit 7. A pulse detection circuit 11 of the extract means 1 extracts a positive polarity pulse S1 from a bipolar clock BCL and a pulse detection circuit 12 extracts a negative polarity pulse S2. The abnormality discrimination means 3 allows a register 32 to shift frequency division data S3 of the pulse S1 by a frequency dividing circuit 31 by using the pulse S2 as a clock and discriminates it to be an error when the shifted result differs from a predetermined value. An abnormality discrimination means 5 allows a register 52 to shift the frequency division data S4 of the pulse S2 by a frequency divider circuit 51 by using the pulse S1 as a clock and discriminates it to be an error when the shifted result differs from a predetermined value.
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Inventors:
TAKAHASHI YASUNORI
Application Number:
JP1160195A
Publication Date:
December 13, 1999
Filing Date:
January 27, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H04L25/49; G06F1/04; H03K5/19; H04L7/00; H04L7/08; H04L25/02; H04L25/34; (IPC1-7): H04L25/49; H04L7/00; H04L7/08; H04L25/02
Domestic Patent References:
| JP63185247A | ||||
| JP5690659A | ||||
| JP62181055U |
Attorney, Agent or Firm:
Umeo Yamauchi
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