PURPOSE: To reduce a delay time and to increase a highest frequency division frequency by switching a current switching control transistor(Tr) from a slightly-ON state into a strongly-ON state when a complementary clock signal is switched.

CONSTITUTION: When a clock signal T and the inverted signal T are switched to an L or an H level corresponding to each other in a master stage circuit 1, a differential input TrQ1 is turned off and a TrQ2 is turned on. In this case, any of current switching control TrsQ5, Q6 with a higher base potential is switched from the slightly-ON state into the strongly-On state. In a slave stage circuit 2, similarly to the case with the circuit 1, when the clock signal T and the inverted signal T are switched to an L or an H level corresponding to each other, any of current switching control TrsQ10-Q13 is switched from the slightly-ON state into the strongly-ON state. The delay time attended with the operation is less and the maximum frequency division frequency is increased almost without increasing the current consumption.