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Title:
BIPOLAR MOS SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS56100460
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of process and improve the degree of integration by forming diffusely a well region on the side of MOSFET and a region separating a bipolar transistor and MOS from each other simultaneously when the transistor and MOS are formed in the same semiconductor substrate.

CONSTITUTION: In an n- type Si substrate 11 are formed diffusely n+ type embodded regions 12a and 12b, whereon an n type layer 13 is made to grow epitaxially, while in one region 12a to form the MOS side the p- type well region 15 is formed diffusely in the layer 13. At the same time, the p- type separating region 16 surrounding the regions 12a and 12b are formed diffusely as far as it reaches the substrate 11, and the layer 13 is separated into islandlike parts containing the regions 12a and 12b respectively. Next, a p+ type base region 17 is formed diffusely within the islandlike layer 13a on the bipolar side including the region 12b, while a ring-shaped p+ type region 18 for preventing parasitic MOS is also formed diffusely within the separating region 16, and on the bipolar side an n+ type emitter region 19 and a collector contact part 20 are provided simultaneously. In addition, on the MOS side, an n+ type source region 21 and a drain region 22 are formed by simultaneous diffusion.


Inventors:
HAIJIMA MIKIO
Application Number:
JP206380A
Publication Date:
August 12, 1981
Filing Date:
January 14, 1980
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L29/78; H01L21/331; H01L21/8249; H01L27/06; H01L29/73; (IPC1-7): H01L27/06; H01L29/72; H01L29/78



 
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