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Title:
BIPOLAR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS59113658
Kind Code:
A
Abstract:

PURPOSE: To enable to obtain the high hFE and fT characteristics in regard to a lateral transistor without increasing the transistor manufacturing process by a method wherein a vertical pnp transistor and the lateral npn transistor are formed on an n type substrate.

CONSTITUTION: A vertical pnp transistor consisting of a p type collector 13, an n+ type base 14 and a p+ type emitter 15, and a lateral npn transistor consisting of n+ type collectors 16, p+ type bases 17 and an n+ type emitter 18 are formed in a p type epitaxial layer 12 on an n type substrate 11. At the bipolar transistor device using the n type substrate thereof, width of the base of the lateral transistor is controlled by accuracy of processing of a photo mask and a photo resist and by depths of the n type diffusion layers, and the values of the hFE and the fT can not be enlarged. However, generally from the difference of mobilities of majority carriers, the high hFE and fT characteristics can be expected in regard to the lateral npn transistor as compared with a lateral pnp transistor, and inconvenience on the circuit design can be reduced.


Inventors:
HORI TAKASHI
Application Number:
JP22436182A
Publication Date:
June 30, 1984
Filing Date:
December 20, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/331; H01L21/8224; H01L21/8228; H01L27/082; H01L29/73; (IPC1-7): H01L27/08; H01L29/72
Attorney, Agent or Firm:
Toshio Nakao



 
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