Title:
BIPOLAR TRANSISTOR AND FABRICATION THEREOF
Document Type and Number:
Japanese Patent JP3191479
Kind Code:
B2
Abstract:
PURPOSE: To decrease base/collector junction capacitance in N type epitaxial layer.
CONSTITUTION: Bird's beak part of SiO2 isolation region 7 is etched except the silicon nitride 5 covering a base window used as a mask in selective oxidation thus providing the edge part of the base window. P type polysilicon 10 for leading out the base is buried in the SiO2 isolation region 7 and the gap part between an N type epitaxial layer 3 and the silicon nitride 5 and then a base out-diffusion layer is formed by self-aligning technology. A BSG film 12 is buried in the gap part of emitter window between the N type epitaxial layer 3 and the silicon nitride 5 and then a link base diffusion layer 15 is formed by self-aligned technology.
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Inventors:
Hiroshi Hirabayashi
Application Number:
JP7597693A
Publication Date:
July 23, 2001
Filing Date:
April 01, 1993
Export Citation:
Assignee:
NEC
International Classes:
H01L29/73; H01L21/331; H01L29/732; (IPC1-7): H01L21/331; H01L29/73
Domestic Patent References:
| JP61290761A | ||||
| JP2183540A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)