Title:
D/E BIT COLLATING DEVICE FOR ISDN CIRCUIT
Document Type and Number:
Japanese Patent JP2843707
Kind Code:
B2
Abstract:
PURPOSE: To simply and accurately decide with collation whether the D bit put on a T line is correctly copied to the E bit put on an R line or not in regard of the pulse signals which are put into prescribed frames which are transmitted on the R and T lines.
CONSTITUTION: The bit extracting circuits 12a and 12b extract each E bit of the pulse signals put on an R line 3a and each D bit of the pulse signals put on a T line 3b respectively. A bit collating circuit 13 detects whether the bit data on the bit data signals (b) and (d) outputted from the circuits 12a and 12b are coincident with each other or not. If not, the circuit 13 decides the noncoincident information as the valid information only in a period when a signal circuit normally keeps a starting state.
Inventors:
SATO MITSUO
TAGUCHI MAKOTO
KUMAGAI RIICHI
TAGUCHI MAKOTO
KUMAGAI RIICHI
Application Number:
JP9830692A
Publication Date:
January 06, 1999
Filing Date:
April 17, 1992
Export Citation:
Assignee:
ANRITSU KK
International Classes:
H04M3/22; H04L12/02; H04L69/40; H04M1/24; H04M11/00; H04Q3/42; H04Q5/00; (IPC1-7): H04M11/00; H04L12/02; H04L29/14; H04M1/24; H04M3/22
Domestic Patent References:
| JP4240937A | ||||
| JP4237234A | ||||
| JP399552A | ||||
| JP63227247A | ||||
| JP62200858A |
Attorney, Agent or Firm:
Takehiko Suzue