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Title:
BIT ERROR DISTRIBUTION MEASURING APPARATUS
Document Type and Number:
Japanese Patent JPS63113367
Kind Code:
A
Abstract:

PURPOSE: To enable quantitative determination of distribution characteristic of the number of bit errors in a block, by measuring the number of errors per block for blocks with a fixed sample to perform a statistic processing.

CONSTITUTION: A frame counter 102 counts clocks 101 to output frame pulses 103 per block as preset and a delay circuit 104 outputs a clear pulse 105 delayed by one time slot from the frame pulses. On the other hand, an error counter 202 counts and outputs error pulses 201, for example, by the clocks and a block counter 204 adds up errors in one frame to output the number of errors within one block. Then, a CPU300 reads out an output of the block counter 204 and performs a statistic processing of the results thereby enabling the measuring of bit errors with a block as a unit, as set according to the block length in the error correction.


Inventors:
AIKAWA SATOSHI
SAITO YOICHI
Application Number:
JP25831286A
Publication Date:
May 18, 1988
Filing Date:
October 31, 1986
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G01R31/00; H04L1/00; H04L1/20; (IPC1-7): G01R31/00
Domestic Patent References:
JPS5261407A1977-05-20
JPS56107117A1981-08-25
JPS58137708A1983-08-16
JPS61287346A1986-12-17
JPS5673938A1981-06-19
Attorney, Agent or Firm:
Takashi Honma



 
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