To improve the measurement processing efficiency of error measurement by providing a deciding means, etc., which decides to fail an input signal in a timing when an error carrier signal is outputted from an error number counter or decides to pass it in a timing when a clock carrier signal is outputted from a clock number counter.

When a synchronous control circuit 11 inputs a synchronization establishment signal (d), a measurement control part 13 sends a measurement start signal (f) to an error number counter 12 and a clock number counter 10. Then, 1st and 2nd FFs of a decision logic circuit 14 are returned to a reset state and also, the counters 12 and 10 start to count error signal (e) numbers and clock numbers. When the bit error rate of an input signal (a) becomes threshold or more, the counter 12 outputs an error carrier signal (g) before the counter 10 outputs a clock carrier signal (h).