To provide a bit phase detection circuit which is never affected by the phase margin of a DFF (D type flip-flop) circuit by acquiring an AND between the pulse and clock signals corresponding to the changing point of a data signal and outputting the propriety of phase relation between the data and clock signals.

A data changing point detection circuit consists of a delay circuit 3 and an EXOR circuit 4 and outputs a detection signal E. In this bit phase detection circuit, the changing point of a data signal D1 is detected by the circuit 4 as a pulse 1 of the signal E. An AND circuit 5 acquires an AND between the pulse 1 and 1 of a clock signal CK. Therefore, a phase detection signal S is always kept at 0 as long as 1 of the signal CK is separate from the signal D1. If 1 of the signal CK is close to the edge of the signal S, the pulse 1 is generated from the signal S to decide that the signal D1 is close to the edge of the clock CK.