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Patent Searching and Data


Title:
BIT RATE COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JPH05207436
Kind Code:
A
Abstract:

PURPOSE: To obtain average compression data quantity with simple circuit configuration.

CONSTITUTION: Code length data ROMs 11, 12 and an adder 13 obtain code length data representing a code length of an unequal length code corresponding to a video data signal. Zero comparators 16, 17 detect a zero of the video data signal and output a zero value detection signal. Zero counters 21, 22 count the number of times of production of the zero detection signal and output zero occurrence data representing a zero production value. A block counter 25, latch circuits 26, 27 and an adder 28 latch and output the zero occurrence data in the unit of the number of prescribed data tentatively. A subtractor 30 subtracts zero number data from code length data in the unit of the number of data to output subtraction data. An integration adder 31 integrated subtraction data and outputs the integration data. The latch circuit 33 latches the integration data in the unit of a prescribed frame as mean compression data quantity.


Inventors:
KATSUBE RYOJI
ITO NOBUYOSHI
OKAMURA HIROSHI
Application Number:
JP1278092A
Publication Date:
August 13, 1993
Filing Date:
January 28, 1992
Export Citation:
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Assignee:
NEC CORP
JAPAN BROADCASTING CORP
International Classes:
H04N19/00; H04N19/42; H04N19/423; H04N19/85; H04N19/91; (IPC1-7): H04N7/13
Attorney, Agent or Firm:
Yosuke Goto (2 outside)