Title:
ビット同期回路および光伝送システム局側装置
Document Type and Number:
Japanese Patent JP4279611
Kind Code:
B2
Abstract:
A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.
Inventors:
Yusuke Yajima
Yoshihiro Ashi
Toru Kazawa
Yoshihiro Ashi
Toru Kazawa
Application Number:
JP2003171680A
Publication Date:
June 17, 2009
Filing Date:
June 17, 2003
Export Citation:
Assignee:
Hitachi Communication Technology Co., Ltd.
International Classes:
H04L7/02; H04B10/272; H04B10/29; H04B10/556; H04L7/033; H04L7/04; H04L25/06; H04J3/06
Domestic Patent References:
| JP2001036511A | ||||
| JP4347931A | ||||
| JP10327159A | ||||
| JP10056446A | ||||
| JP8321827A | ||||
| JP10327136A | ||||
| JP8256137A |
Attorney, Agent or Firm:
Polaire Patent Business Corporation
Katsuo Ogawa
Kyosuke Tanaka
Katsuo Ogawa
Kyosuke Tanaka
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