PURPOSE: To lower the operating frequency of the circuit to make the circuit constitution easy and to reduce power consumption by providing plural oscillation circuits whose oscillating frequency differs, and selecting an oscillation circuit minimizing the frequency difference between input and output.

CONSTITUTION: A phase difference between an NRZ signal inputted from an input terminal 11 and a recovered clock is compared by a phase comparator 13, which outputs the result of phase comparison. A U/D counter 14 integrates the result of phase comparison outputted from the phase comparator circuit 13 and outputs a control pulse to an oscillation circuit selector 15 and is reset when a prescribed value is integrated. Upon the receipt of a control pulse, the oscillation circuit selector 15 integrates the pulse. When frequencies between the input and output have a difference, since the control pulse is consecutive unidirectionally, the integration value is increased to a value and the oscillation circuit selector 15 selects one of oscillation circuits 16a-16n so as to decrease the difference of the frequencies. Thus, the operating frequency of the circuit is lowered, the circuit constitution is facilitated and power consumption is reduced.