To reset two timing signals to a prescribed phase in the case of external reset operation.

A timing generating circuit 100 generates timing signals M, L with a 5-bit width and a data transfer circuit 102 uses the signals M, L to replace a clock signal of input data. A caption DFF is a D flip-flop and a caption 2DFF is a series connection circuit of two DFFs, and the DFF and quinary ring counters 5,11 are operated at a falling edge of an input clock. Upon the receipt of a reset pulse, an external reset position adjustment means 50 compares a phase of a signal T with a phase of a signal P, and an S-R flip-flop 18 and a multiplexer 15 give the signal R to the counter 5 when the signal T is faster and gives the signal R to the counter 5 for resetting when the signal P is faster. The counter 11 is reset, faster at all times by the counter 5 and the signals M, L have a prescribed phase.