To provide a bit timing reproducing circuit with which the degradation of characteristics caused by noises or non-linear distortion can be prevented.

The real part signal of a complex modulated signal in a base frequency band is converted into a real part digital signal by a first A/D converter 10 and converted into an imaginary part digital signal by a second A/D converter 11, and a modulated signal phase detecting circuit 14 detects the phase angle of the complex modulated signal in the base frequency band on a complex plane from the real part digital signal and the imaginary part digital signal and outputs phase angle information. Then, the phase angle information is delayed just for a symbol interval by a delay circuit 16, a clock phase deviation information is outputted to first and second interpolation filters 18 and 19 by a clock phase detecting circuit 17 from a phase angle difference provided by subtracting the phase angle information and the delayed phase angle information through a subtracter 15, and the real part digital signal and the imaginary part digital signal are respectively converted into signals at the optimum sampling point.