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Title:
BLOCK MATCHING ARITHMETIC UNIT AND RECORDING MEDIUM STORING PROGRAM AND READ BY MACHINE
Document Type and Number:
Japanese Patent JPH1141604
Kind Code:
A
Abstract:

To execute a block matching arithmetic processing at a high speed while inputting/outputting word data including data of plural pixels in the block matching arithmetic unit.

A right-rotation shift current block generating means 4 generates a right-rotation shift current block by rotating a current block to the right by two pixels each and stores the result to a current block storage part 10, a left-shift reference generating means 6 generates a left-shift reference area by shifting a reference area to the left by one pixel and stores it to a reference area storage part 11, a partial block matching arithmetic means 7 to execute block matching arithmetic processing in parallel for each partial block by dividing a block into two columns to obtain partial block matching arithmetic data. A total sum arithmetic means 9 selects partial block matching arithmetic data relating the same motion vector and calculates the total sum to obtain the block matching arithmetic processing result.


Inventors:
MIYAZAKI TAKASHI
Application Number:
JP21007797A
Publication Date:
February 12, 1999
Filing Date:
July 18, 1997
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04N19/50; G06T7/20; H04N5/14; H04N19/119; H04N19/134; H04N19/136; H04N19/139; H04N19/176; H04N19/196; H04N19/42; H04N19/423; H04N19/436; H04N19/503; H04N19/51; H04N19/57; (IPC1-7): H04N7/32
Attorney, Agent or Firm:
Sakai Hiromi