PURPOSE: To simplify a block selecting circuit while preventing malfunction by using a few address lines from the lowest-order and highest-order ones as memory- unit selection lines and block selection lines.

CONSTITUTION: For addition by block selection switches in each memory unit, S2 is a one-bit adder, S3 is a two-bit adder and S4WS7 are three-bit adders. Blocks B1WB8 are selected by comparing circuits C1WC8. The number of address lines A is three and when those three lines are all held at "0", the selection state is set. As for four memory units, although memory blocks B1WB8 may be selected in parallel, only one unit is enabled by selecting circuits composed of SW1WSW7, S2WS7 and C2WC8 to operation and in or from one address information is written or read. The high-order three lines are used as block selection lines, the need for an address setting switch is eliminated and setting errors are also eliminated, so that the block selecting circuit can be simplified.