Title:
BLOCK TRANSFER CIRCUIT
Document Type and Number:
Japanese Patent JPH01205259
Kind Code:
A
Abstract:
PURPOSE:To efficiently execute a data transfer by simultaneously copying the data of a shared memory to plural local memories by means of a transfer once in the data transfer between one shared memory and plural local memories. CONSTITUTION:The title circuit is composed of processor modules 1 and 2, a bus arbiter 3, and a shared image memory module 4 to have a shared image memory 13 as one shared memory. According to data transfer requests from processors 21 and 22, a batch data transfer is executed between one shared memory 13 and plural local memories 11 and 12. Consequently, the same contents can be simultaneously copied to plural local memories 11 and 12 by transferring once. Thus, the data transfer can be efficiently executed.
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Inventors:
IWASHITA MASAO
Application Number:
JP2872788A
Publication Date:
August 17, 1989
Filing Date:
February 12, 1988
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F15/17; G06F13/38; G06F15/16; (IPC1-7): G06F13/38; G06F15/16
Domestic Patent References:
| JPS61118859A | 1986-06-06 | |||
| JPS6146552A | 1986-03-06 | |||
| JPS62108351A | 1987-05-19 |
Attorney, Agent or Firm:
Yoshiyuki Iwasa