Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3206541
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To quickly switch a defective cell array generated in a cell array to a redundant cell array without increasing any circuit scale.
SOLUTION: This device is provided with an R/N switching setting circuit 140 in which a plurality of transistors in a conductive state in a normal time are serially connected. When an H level YPR indicating the use of a redundant cell and the array position of a defective cell at that time are outputted from a redundancy judging circuit 120 for inputting an address, and judging the use and non-use of the redundant cell, the array position is set through a redundant position decoder 130 in the switching setting circuit 140. The switching setting circuit 140 generates each switching signal DSW based on the array position, and outputs it to an R/N switching circuit 150. The switching circuit 150 switches and connects each I/O of an inputting and outputting part 160 with each cell of a memory block selected according to the address based on each inputted switching signal.
Inventors:
Tomohiro Tsuchiya
Application Number:
JP5193398A
Publication Date:
September 10, 2001
Filing Date:
March 04, 1998
Export Citation:
Assignee:
NEC
International Classes:
G11C29/04; G11C29/00; (IPC1-7): G11C29/00
Domestic Patent References:
| JP3176899A | ||||
| JP2208898A | ||||
| JP668693A |
Attorney, Agent or Firm:
Masaki Yamakawa