Title:
接合材評価方法、及び評価試験装置
Document Type and Number:
Japanese Patent JP7338258
Kind Code:
B2
Abstract:
To properly evaluate degradation of a joint material which joints a semiconductor chip and a substrate to each other.SOLUTION: There is provided a method for evaluating a joint material for evaluating degradation in a joint material 103 for jointing a semiconductor chip 101 and a substrate 102 to each other, the method including: a setting step of setting an evaluation body 100 in a setting space R between an upper pressure application jig 2 and a lower pressure application jig 3; a pressure application step of applying a pressure on an evaluation body 100 by a pressure application mechanism 4; a voltage application step of applying a voltage to the semiconductor chip 101 of the evaluation body 100 with a pressure being applied thereon by the pressure application mechanism 4; and an evaluation step of evaluating degradation in the joint material 103 after the application of the voltage.SELECTED DRAWING: Figure 2
Inventors:
Masao Negishi
Takeo Nakako
Chie Sugama
Yuki Kawana
Yanaka Yuichi
Yoshinori Ejiri
Takeo Nakako
Chie Sugama
Yuki Kawana
Yanaka Yuichi
Yoshinori Ejiri
Application Number:
JP2019113825A
Publication Date:
September 05, 2023
Filing Date:
June 19, 2019
Export Citation:
Assignee:
Resonac Co., Ltd.
International Classes:
G01R31/28; G01N17/00; H01L21/52
Domestic Patent References:
| JP2006053052A | ||||
| JP6384979B1 | ||||
| JP2002289995A | ||||
| JP2018173357A | ||||
| JP2010147426A | ||||
| JP2011082482A | ||||
| JP2004317394A | ||||
| JP6118105A | ||||
| JP2019021740A |
Foreign References:
| US5945834 |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshinori Shimizu
Hiroyuki Hirano
Yoshinori Shimizu
Hiroyuki Hirano
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