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Title:
BONDING STRUCTURE OF ELECTRONIC COMPONENT
Document Type and Number:
Japanese Patent JPH1012664
Kind Code:
A
Abstract:

To provide a bonding structure of an electronic component, which can facilitate wiring of routed wires of a sub circuit substrate and also can reduce the size of the sub circuit substrate at the time of mounting a semiconductor chip on a main circuit substrate through the sub circuit substrate.

An outer connecting electrode 34 of a TAB substrate 31 having a semiconductor chip 21 mounted thereon is bonded to a first connecting electrode 44 of a sub circuit substrate 41. In this case, the first connecting electrode 44 is disposed between a central part of an array of second connecting electrodes 45 and a peripheral part of an array of second connecting electrodes 46 on an upper surface of the sub circuit substrate 41. Accordingly, routed wires 48 and 47 for electrically connecting the first and second connecting electrodes 44 and 46, 45 are divided as directed toward the central part side and peripheral part side, so that the routing can be facilitated. Further, the sub circuit substrate 41 can be made small in size.


Inventors:
KUSAKA TOSHIKI
IGAWA OSAMU
Application Number:
JP17719996A
Publication Date:
January 16, 1998
Filing Date:
June 19, 1996
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
H01L21/60; H05K1/14; H05K3/36; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Jiro Sugimura